Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the ...

Functional safety is a major challenge for field programmable gate arrays (FPGAs) and other semiconductor designs. Safety requirements go beyond traditional verification, which focuses on design bugs.

This is the second part of a two-part discussion (Part 1 appeared in August) in which the author considers fault-coverage analysis and simulation for full-scan testing of ASIC designs. These elements ...