EDN

Make an asynchronous clock for VPX-based PCIe systems

The VITA46 VPX standarddefines a chassis that can accommodateall manner of cards with a commonform factor (Reference 1). Thecards plug into a common backplane.This design employs the VITA46.4standard ...
Electronic Design

Choose The Optimum Clock Source For PCI Express Applications

PCI Express is an interface standard developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). Originally designed for desktop personal computers, it’s used across a range ...
EDN

Asynchronous PCI bridge offers a high quality solution with low power consumption.

Tundra Semiconductor Corp. is now in full production of its low power, asynchronous PCI-to-PCI bridge. The Tundra Tsi350™ offers communications and network equipment customers a competitive high ...
Design-Reuse

Asynchronous Logic: large CMOS devices without a clock tree

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...
Design-Reuse

Design Transition from Sync to Async: Design and Verification Challenges

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...
Embedded

Asynchronous reset synchronization and distribution – challenges and solutions

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
Embedded

Asynchronous reset synchronization and distribution – ASICs and FPGAs

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
Electronic Design

Assertions Stand Guard Over SoC Clock Domains

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...