Signal integrity issues such as crosstalk delay and noise are significant challenges for system-on-chip designs at 130 nanometers and below. At such process nodes, preventative measures to mitigate SI ...
Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Experienced designers of 10 Gbits/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/8GFC) products are well aware that the maintenance of signal quality is far more difficult ...
Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...
To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an ...
Conformance tests represent an important milestone during product development. The relevant standardization committees have published detailed test specifications for many interfaces such as USB and ...
Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
The Department of Electrical, Computer, and Energy Engineering has a subplan in High Speed Digital Engineering (HSD) as part of our Professional Master's Program. Students with a bachelor's degree in ...
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