Semiconductor Engineering

Inside UVM

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Semiconductor Engineering

AI Agents For UVM Generation: Challenges And Opportunities

The first major challenge directly comes from the limited data. Unlike software engineering tasks, where large-scale public data is abundant, the hardware domain, especially UVM verification, is ...
Semiconductor Engineering

A Novel Approach For Hardware-Software Co-Verification

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and ...
Semiconductor Engineering

Inside UVM, Take Two

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In ...