EDN

VHDL 101 – From Logic Gates to Adders

VHDL is all about creating logic. As a descriptive language, all the HDL languages bring something unique to programming – making true parallel logic circuit. As we take baby steps into VHDL, we will ...
EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
Design-Reuse

SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology

The growing complexity of SoCs and the reduced life cycle of electronic products demand higher levels of design productivity while meeting compressed development schedules. The reuse of design IP ...