Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

With the shrinking of technology to deeper sub-micron levels, SoC design is getting more complex every day as more functionality gets incorporated into the chips. As SoC designers navigate this ...

The design complexity of sub-micron designs due to ever growing huge number of gates and interactions has made it difficult for physical design tools to handle the physical synthesis or placement and ...