IEEE

28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS

In-Memory Computing (IMC) hardware accelerators for Deep Neural Networks (DNNs) require massive quantity of coefficients stored in a single device to limit performance losses in multicore clusters.
IEEE

Optimized Vedic Multiplier $\mathrm{N}^{\ast}\mathrm{N}$ using Adder Approximations and Modified Carry Look Ahead Adders

Abstract: This paper introduces an innovative approach to enhancing Vedic multipliers using approximate full adders with 2X1 multipliexers. The study compares this novel design with traditional ...